1. Field of the Invention
The present invention relates to a scheme for testing a memory device, and more particularly, to a memory device having a compress test operation and method thereof.
2. Description of the Prior Art
In general, a memory device has many electronic PADs, where data can be written to or read from the memory device via each electronic PAD. As regards an external stress equipment for testing the memory device, it is necessary to test all elements and a storage block on a data read path (or a data write path) corresponding to each electronic PAD, to guarantee that internal elements within the memory device can operate correctly. The stress equipment often writes a test data into the storage block through the data write path and then reads the written test data from the storage block through the data read path. Therefore, if the written test data read from the storage block is detected to be different from the original test data, this means that an error arises in internal element(s) with the memory device.
Please refer to FIG. 1. FIG. 1 is a simplified diagram of a conventional memory device 100 including an electronic PAD 105, a reading and writing circuit 110, and a storage block 115. As shown in FIG. 1, the reading and writing circuit 110 includes a sense amplifier 120, an read/write multiplexer (R/W MUX) 125, an output buffer 130, an off chip driver (OCD) 135, a receiver 140, and a data input register 145. The memory device 100 may further include another sense amplifier (not shown in FIG. 1) positioned between the storage block 115 and the sense amplifier 120. A data read path within the reading and writing circuit 110 is composed of the sense amplifier 120, the R/W MUX 125, the output buffer 130, and the OCD 135; a data write path within the reading and writing circuit 110 is composed of the receiver 140, the data input register 145, the R/W MUX 125, and the sense amplifier 120. For reading data from the memory device 110, the above-mentioned other sense amplifier and the sense amplifier 120 are both utilized for sensing a voltage difference or current difference from a storage cell in the storage block 115 and for amplifying the voltage difference or current difference to output a high voltage level (e.g. 1 V) representative of bit ‘1’ or a low voltage level (e.g. zero) representative of bit ‘0’. At this time, the R/W MUX 125 transmits a signal outputted by the sense amplifier 120 into the output buffer 130; the output buffer 130 then buffers the signal transmitted by the R/W MUX 125 and then outputs the buffered signal into the OCD 135 by a specific queuing scheme (e.g. a first in first out (FIFO) queuing scheme). The OCD 135 adjusts a voltage level of the buffered signal outputted by the output buffer 130 for improving signal quality of a signal finally transmitted to the electronic PAD 105. Accordingly, an external circuit can estimate the data read from the memory device 100 at bit ‘1’ or bit ‘0’ by a voltage level of a signal at the electronic PAD 105. In addition, for writing data into the memory device 100, the receiver 140 is utilized for receiving a signal at the electronic PAD 105 and then outputting the received signal into the data input register 145, which transmits the registered signal into the R/W MUX 125. The R/W MUX 125 outputs the signal transmitted by the data input register 145 into the storage cell in the storage block 115 via the sense amplifier 120 and the above-mentioned other sense amplifier. Therefore, data representative of the signal can be stored in the storage cell.
As described above, when testing the storage block 115 and the data read/write path of the reading and writing circuit 110, the stress equipment also writes the test data into the storage block 115 through the above-mentioned data write path and then reads the written test data from the storage block 115 through the above-mentioned data read path. The test data read from the memory device 100 and the original test data are continuously compared to determine whether an error arises in the internal element(s) within the memory device 100. However, considering the cost of the stress equipment (the cost will become much higher if a number of required test channels are increased by a large amount) and efficiency when testing the memory device 100, the stress equipment may obtain test results with respect to various reading and writing circuits and storage blocks corresponding to various electronic PADs utilizing a single electronic PAD. Consequently, a hardware designer often adds a test circuit into a memory device, where in a compress test mode the test circuit is utilized for comparing different test data (that are transmitted by the reading and writing circuits and the storage blocks corresponding to the electronic PADs) with an original test data to generate a test result (pass or fail) into the single electronic PAD. The stress equipment can therefore obtain the test results with respect to the reading and writing circuits and the storage blocks only utilizing the single electronic PAD. Ideally, by the added test circuit mentioned above, the reading and writing circuits and the storage blocks corresponding to the various electronic PADs can be detected; however, in practice, the test circuit can never detect all elements within the reading and writing circuits corresponding to the electronic PADs (that is, some elements may not be detected) with the result that an error may arise in a particular element within the memory device although the stress equipment obtains a pass test result. If this situation occurs frequently, a yield with regards to products manufactured according to this memory device will be reduced significantly.